As complementary metal-oxide semiconductor (CMOS) static random access memory (SRAM) circuits continue to shrink in accordance with Moore's Law, the inherent variability in the transistors is increasingly influencing the performance and functionality of the SRAM circuits. Thus, obtaining a clear understanding of how much variance these devices possess is valuable to SRAM designers, transistor model designers, and the process engineering groups.
Conventional methods exist to obtain transistor variation information, including probing the transistors in a laboratory. However, this process is very time consuming and expensive and therefore is not widely implemented.